[Development] [OT] Re: 32bit linux build of qt5.10.0 w/ webengine
chgans at gmail.com
Sat Jan 6 11:47:42 CET 2018
On 5 January 2018 at 15:11, Thiago Macieira <thiago.macieira at intel.com> wrote:
> On Thursday, 4 January 2018 23:40:40 -02 Christian Gagneraud wrote:
>> Neatpick: AVX itself doesn't require billions of transistors, the
>> first intel proc to require more than a billion transistor are 4 and 6
>> cores i7.
> Fair enough. The billions are usually due to expanded L3 caches, not the CPU
> itself. I was exaggerating.
or L2, or L1... it all depends on size. Static RAM usually requires 4
transistors per bit, and dynamic RAM only one (on average)
1MB of cache => 4 * 1 * 8 * 1024 * 1024 = 33.5 millions transistors
The more cores on a die, the more L3 cache you need... And nowadays,
50MB of L3 is not that crazy...
This is certainly wrong (i'm not very aware of the latest
technologies), but it should be a "fair" guesstimate.
> Still, AVX and AVX2 are considerable die size (don't know how much).
I've googled for half an hour to find this information and finally
gave up. Since you work for Intel, maybe you could ask one of your
colleague, that's an interesting bit of information.
Since SSE and AVX are just sub-components of a specialised ALU/FPU, I
wouldn't be surprised if they require less than a few thousand
transistors each (they "just" implement specialised operations), and
die size contribution is certainly less than 0.01 % (Wild guess
Another noob question would be how much of them is actually hard-wired
operation vs instruction implemented via ROM microcode.
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