[Interest] Heavily Commented Example: Simple Single Frontend with Two BackendsHi,

Graeme Gill graeme2 at argyllcms.com
Wed Oct 24 22:18:01 CEST 2012

Thiago Macieira wrote:

> I realised this because both ARM and IA-64 -- architectures with weak memory 
> ordering -- have no special instruction for this kind of activity. If all you 
> need is a flag signalling a condition, you'd use the standard "ld1" / "ld4" 
> instruction on IA-64 or the "ldrb" / "ldr" instruction on ARM.

Any popular architecture that supports the notion of shared
memory addressing (ie. all processors see the same memory
map) is highly likely to ensure cache coherence in hardware.

To do otherwise would be to invite great difficulty in
porting software to it.

Graeme Gill.

More information about the Interest mailing list